DUAL NON-VOLATILE MEMORY CELL COMPRISING AN ERASING TRANSISTOR

专利摘要:
The invention relates to a non-volatile memory cell (Ci, j) on a semiconductor substrate, comprising a first transistor (TRi, j) comprising a control gate (CG), a floating gate (FGr) and a drain region ( D), a second transistor (TEi, j) comprising a control gate (CG), a floating gate (FGe) and a drain region (D), in which the floating gates (FGr, FGe) of the first and second transistors are electrically connected, and the second transistor comprises a conductive region (IS, n1) electrically connected to its drain region (D) and extending opposite its floating gate (FGe) via a tunnel dielectric layer (D1).
公开号:FR3021804A1
申请号:FR1454891
申请日:2014-05-28
公开日:2015-12-04
发明作者:Rosa Francesco La；Stephan Niel；Arnaud Regnier
申请人:STMicroelectronics Rousset SAS；
IPC主号:

专利说明:

[0001] The present invention relates to nonvolatile memories and in particular to a memory plane and memory cell structure of the type described in application US 2013/0228846. By way of reminder, FIG. 1 represents such a memory map structure MAO and shows memory cells Mij, Mi-ij, Mij + i, Mi_i j + 1 of the aforementioned type, here belonging to two adjacent physical pages Pi, Pi_1 of memory plane, of respective ranks "i" and "i-1". The memory cells Mij, Mi-ij, Mij + 1, Mi_ij + i are accessible in reading and writing via bit lines BLj, BLi + i, a word line WLi_i j and control lines of CGLi grid, CGLi_i. Each memory cell comprises a floating gate transistor, respectively Tij, Ti-ij, Tij + i, Ti_i j + 1. The drain terminals D of the transistors Tij, Ti_i j are connected to the bit line BLi and the drain terminals of the transistors Tij + i, Ti_ij + i are connected to the bit line BLj_pi. The control gates CG of the transistors Tij, Tij_pi are connected to the gate control line CGLi and the control gates CG of the floating gate transistors Ti_ij, Ti_i j + 1 are connected to the gate control line CGL 1.
[0002] Each floating gate transistor Tij j-pi also has its source terminal connected to a source line SL via a selection transistor ST. The selection transistors ST memory cells Mij and j share the same CSG control grid and the two memory cells are, therefore, called "binoculars". Likewise, memory cells Mij + i and j + 1 are twin memory cells and their selection transistors ST have a common control gate CSG. Each common control gate is preferably a vertical gate buried in a substrate receiving the MAO memory plane, the source line SL being also a buried line. These CSG common control grids, or twin memory cell selection grids, are connected to the word line WL1-1,1. Such memory cells are erased or programmed by the channel, that is to say by carrying the substrate at a positive erase or negative programming voltage causing the extraction of electric charges from their floating gates or the injection of electric charges in their floating gates, by Fowler-Nordheim effect.
[0003] More particularly, the erasure of a memory cell is ensured by combining the positive voltage applied to the substrate to a negative voltage applied to the control gate of its floating gate transistor, while the control gate of the gate transistor. The floating cell of the twin memory cell receives a positive erase inhibit voltage to prevent it from being simultaneously erased (Fig. 11 of the aforementioned application). Likewise, the programming of a memory cell is ensured by combining a negative voltage applied to the bit line of the memory cell and the substrate, to a positive voltage 1 () applied to the control gate of its floating gate transistor. while the control gate of the floating gate transistor of the twin memory cell receives a negative programming inhibit voltage to prevent it from being simultaneously programmed (Fig. 12 of the aforementioned application).
[0004] Finally, the reading of a memory cell is ensured by applying a positive voltage to the control gate of its floating gate transistor, as well as a positive voltage to the corresponding bit line, while the twin memory cell, which is connected to the same bit line, receives on its control gate a negative reading inhibition voltage to prevent it being simultaneously read (Fig 9 of the aforementioned request).
[0005] This memory plane structure having twin memory cells comprising a shared vertical selection grid and buried in the substrate, has the advantage of being of a small footprint. The channel erasure method that they require is well suited to achieving a page-erasable memory array, but is less amenable to making a word-erasable memory array. This appears by comparing the word-erasable memory array shown in FIG. 24 of the aforementioned application to the erasable memory array per page shown in FIG. 23 of this application, the first being more complex than the second. Thus, for the memory map to be word-erasable, each CGL grid control line, instead of being connected to all the memory cells of a page, must be divided into a plurality of control lines. grid one grid control line per word. This results in a significant complexity of word and column line decoders, and requires the provision of various voltage switches to control, within each page, the grid control lines of the different words.
[0006] It may therefore be desirable to provide an improvement of this memory and memory cell structure which is more suitable for the implementation of a word-erasable memory, and does not lead to a complication of the control elements. of the memory map.
[0007] This conventional memory array and memory cell structure also requires providing a word line decoder capable of applying a positive read voltage to a memory cell to be read while applying a negative read inhibit voltage to its memory cell. twin memory cell, as mentioned above.
[0008] It may therefore also be desirable to provide another improvement of this memory and memory cell structure which makes it possible to read a memory cell without applying a negative voltage to the twin memory cell.
[0009] Embodiments of the present invention relate to a non-volatile memory cell on a semiconductor substrate, comprising a first floating gate transistor having a control gate, a floating gate and a drain region, a second floating gate transistor comprising a control gate, a floating gate and a drain region, wherein the floating gates of the first and second floating gate transistors are electrically connected, and the second floating gate transistor comprises a conductive region electrically connected to its drain region. and extending opposite its floating gate via a tunnel dielectric layer. According to one embodiment, the floating gates of the first and second floating gate transistors are formed by a same layer of conductive material. According to one embodiment, the conductive region is a doped region of the substrate. According to one embodiment, the memory cell comprises at least one selection transistor connecting a source region of the first floating gate transistor to a source line. According to one embodiment, the selection transistor comprises a vertical control gate buried in the substrate.
[0010] Embodiments of the invention also relate to a nonvolatile memory on a semiconductor substrate, comprising at least one memory cell according to the invention, a first bit line electrically connected to the drain region of the first transistor. floating gate, and a second bit line electrically connected to the drain region of the second floating gate transistor. According to one embodiment, the memory comprises means for deleting the Fowler Nordheim memory cell, configured to extract negative electric charges from the floating gate of the second floating gate transistor via the conductive region. According to one embodiment, the memory comprises means for programming the Fowler Nordheim memory cell, configured to inject negative electric charges into the floating gate of the second floating gate transistor via the conductive region. According to one embodiment, the memory comprises means for programming the memory cell by hot electron injection, configured to inject negative electrical charges into the floating gate of the first floating gate transistor by means of a current flowing in the transistor. According to one embodiment, the memory comprises means for reading the memory cell via the first floating gate transistor.
[0011] According to one embodiment, the memory comprises a first memory cell according to the invention and a second memory cell of the same structure as the first memory cell, having a selection transistor having the same control gate as the selection transistor of the first memory cell.
[0012] According to one embodiment, the memory comprises a bit line electrically connected to the drain region of the first floating gate transistor of the first memory cell, another bit line electrically connected to the drain region of the first gate transistor. floating point of the second memory cell, and yet another bit line electrically connected to both the drain region of the second floating gate transistor of the first memory cell and the drain region of the second floating gate transistor of the first memory cell. second memory cell.
[0013] Embodiments of the invention also relate to a method of manufacturing on a semiconductor substrate of a memory cell according to the invention, comprising the steps of forming in the substrate insulating trenches delimiting at least a first and a second substrate strip, doping the second substrate strip to make it conductive, forming on the substrate a floating gate arranged transversely to the two substrate strips, with the interposition of a first dielectric layer, forming a control gate on the gate floating with interposing a second dielectric layer, to obtain a stack of grids, and doping the two substrate strips on each side of the gate stack, to reveal drain and source regions of the first gate transistor floating and at least one drain region of the second floating gate transistor, the conductive region facing the floating gate of the second floating gate transistor being formed by a region of the second doped substrate band before the formation of the gate stack.
[0014] According to one embodiment, the method comprises a step of forming in the substrate a conductive trench arranged transversely to the substrate strips and forming, after doping the two substrate strips, a buried vertical grid of a selection transistor of the memory cell.
[0015] Embodiments of the invention also relate to a method of erasing a nonvolatile memory cell on a semiconductor substrate, the memory cell comprising a first floating gate transistor having a control gate, a floating gate, a dielectric layer tunneling between the floating gate and the substrate, a drain region and a source region, the method comprising the steps of: providing a second floating gate transistor having a control gate, a floating gate and a gate region; drain, connect the floating gates of the first and second floating gate transistors, provide in the second floating gate transistor a conductive region electrically connected to its drain region and extending opposite its floating gate via a tunnel dielectric layer, and apply a negative electrical potential difference between the grid of co and controlling the drain region of the second floating gate transistor to extract negative electrical charges from the floating gate of the second floating gate transistor through the conductive region.
[0016] According to one embodiment, the method comprises the steps of providing a first bit line electrically connected to the drain region of the first floating gate transistor, providing a second bit line electrically connected to the drain region of the second floating gate transistor, providing a gate control line electrically connected to the control gates of the first and second floating gate transistors, and applying the negative electrical potential difference between the control gate and the drain region of the second transistor floating gate via the gate control line and the second bit line. Embodiments and methods of manufacturing a memory array structure and memory cells according to the invention, as well as methods for reading and writing memory cells according to the invention, will be described in the following in with reference to the accompanying drawings, in which: - Figure 1 previously described is the electrical diagram of a conventional structure of memory plane and memory cell, - Figure 2 is the electrical diagram of a first embodiment FIG. 3 is a sectional view of a memory cell of FIG. 2; FIG. 4 is a further sectional view of a memory plane structure and a memory cell according to a first improvement according to the invention; of the memory cell; FIG. 5 shows voltages applied to the memory array of FIG. 2 for erasing a memory cell; FIG. 6 is a sectional view of a memory cell of FIG. 5; and show e of the voltages applied to the memory cell, - Figure 7 is another sectional view of the memory cell, and shows the voltages applied to the memory cell, - Figure 8 shows voltages applied to the memory plane of Figure 2 for FIG. 9 is a sectional view of a memory cell of FIG. 8 and shows the voltages applied to the memory cell, FIG. 10 is another view of a memory cell of Fowler Nordheim effect. FIG. section of the memory cell and shows the voltages applied to the memory cell, FIG. 11 shows voltages applied to the memory array of FIG. 2 for the programming of a memory cell by hot electron injection, FIG. 12 FIG. 13 shows the voltages applied to the memory array of FIG. 2 for reading a memory cell. FIG. 14 is a sectional view of a memory cell of FIG. 13 and shows voltages applied to the memory cell; FIGS. 15 to 24 show steps of a method of manufacturing a cell; FIG. 25 is a circuit diagram of a memory comprising the memory plane of FIG. 2; FIG. 26 is a circuit diagram of a second embodiment of a structure. FIG. 27 is a circuit diagram of a first embodiment of a memory plane and memory cell structure according to a second improvement according to the invention; Figs. 28 to 32 show steps of a method of manufacturing a memory cell shown in Fig. 27; Fig. 33 shows voltages applied to the memory array of Fig. 27 for reading a memory cell; Figure 34 The sch electrical ema of a memory comprising the memory plane of FIG. 27; FIG. 35 is the electrical diagram of a second embodiment of a memory plane and memory cell structure according to the second improvement.
[0017] FIG. 2 is the electrical diagram of an embodiment of two memory cells C14, 1 and a memory plane MA1 according to a first improvement according to the invention of the memory and memory cell structure of FIG. 1. The memory cells are read and write accessible via a first RBL bit line, a second EBL bit line, a WL word line, and two CGL gate control lines. ,. The memory cell belongs to a physical page P, of the memory plane and the memory cell C, j belongs to an adjacent page 13, 4. The pages 131_1 can include various other memory cells and the memory plane MA1 can include various other pages.
[0018] The memory cell comprises two floating gate transistors TR, J, TE, J whose floating gates FGr, FGe are interconnected, the floating gate transistor TR, J being dedicated to the reading of the transistor memory cell and the gate transistor. floating TE, J dedicated to erasing the memory cell. In one embodiment, the interconnection 35 of the floating gates FGr, FGe is ensured by manufacturing the two floating gates from the same conductive element CFG.
[0019] The TRIJ transistor has a control gate CGr connected to the gate control line CGL1, a drain terminal D connected to the bit line RBLJ and a source terminal S connected to the drain terminal D of a transistor ST selection whose source terminal S 5 is connected to a source line SL. The transistor TEIJ has a control gate CGe connected to the gate control line CGL1, a drain terminal D connected to the bit line EBLJ and a source terminal S connected to the drain terminal D of a selection transistor ST whose source terminal S is connected to a source line SL.
[0020] The memory cell Ci_i j has the same structure as the memory cell C, J and comprises two floating gate transistors TR j, j whose floating gates FGr, FGe are interconnected and / or formed by the same conductive element CFG. The transistor TRi_i ja a control gate CGr connected to the gate control line CGLi_i, a drain terminal D connected to the bit line RBLJ and a source terminal S connected to the drain terminal D of a transistor of ST selection whose source terminal S is connected to a source line SL. The floating gate transistor TEl_i ja a control gate CGe connected to the gate control line CGLi_i, a drain terminal D connected to the bit line EBLJ and a source terminal S connected to the drain terminal D of a ST selection transistor whose source terminal S is connected to a source line SL.
[0021] The selection transistors ST associated with the floating gate transistors TRIJ, j have a common control gate CSG connected to the word line WL14,1, which is preferably made in the form of a vertical grid buried in a substrate receiving the memory map MAO. Likewise, the selection transistors ST associated with the floating gate transistors TEIJ, j have a buried vertical common control gate CSG which is connected to the word line WL14,1. The memory cell Cij is therefore, structurally, the equivalent of the combination of memory cells Mij, MI, J + 1 shown in Figure 1, whose floating gates were electrically connected. Similarly, the memory cell Cgi_ij is, structurally, the equivalent of the combination of memory cells Mi-u, 1 41-1J + 1 shown in Figure 1 whose floating gates were electrically connected. The two memory cells can therefore be called "dual" memory cells. Their selection transistors ST having two by two the same control grid, these memory cells can also be called "twin" memory cells.
[0022] The floating gate transistor TE, J, however, differs from the floating gate transistor T, J +, of the memory cell M, J + 1 in that it comprises a conductive region IS extending in front of its gate. FGe floating with interposition of a tunnel dielectric layer, and which is electrically connected to its drain terminal D. Similarly, the floating gate transistor TE, _, j differs from the floating gate transistor Ti_u_pi of the memory cell 1 4.4 j + i in that it comprises a conductive region IS which extends in front of its floating gate FGe via a tunnel dielectric layer, and which is electrically connected to its drain terminal D. Fig. 3 is a sectional view of an embodiment of transistors TE, J, TE, 4 and their respective selection transistors ST. The floating gate transistors are made on a substrate PW, for example silicon, forming the upper region of a WF semiconductor chip. The WF chip is initially a wafer on which several integrated circuits are made, which is then cut into individual chips.
[0023] The source lines SL of the selection transistors ST are formed by a deep doped region n0 which here forms a collective source plane for the entire memory plane. The common control gate CSG of the selection transistors ST is formed with a conductive material, for example polysilicon (polycrystalline silicon), deposited in a trench made in the substrate, and isolated therefrom by a dielectric layer OD. This "conducting trench" also forms the word line WL, 4 ,, along an axis perpendicular to the plane of the figure. The floating gates FGe of the transistors TE, J, TE, 4 j are arranged on each side of the trench CSG, and rest on the substrate PW via a tunnel dielectric layer D1. They are formed here by a conductive part, for example made of polysilicon, which extends to the transistors TR, J, TR, 4 j (not visible in this sectional plane, see Fig. 4) to form also the grids floating of these transistors.
[0024] The control gates CGe of the transistors TE, J, TE, 4 j extend above the floating gates via a dielectric layer D2. They are formed here by conductive strips of polysilicon which also form the CGL 'CGL gate control lines, 4 along an axis perpendicular to the plane of the figure.
[0025] N 2 and n 3 doped regions implanted on each side of the gate stack FG / CGe respectively form the drain (D) and source (S) regions of the transistors TE, J, TE, the n3 regions also forming the drain regions (D) of the selection transistors ST. The source regions (S) of the selection transistors ST are here formed by the nO layer, the CSG common vertical gate of the selection transistors extending here to the nO region. In an alternative embodiment, the lower end of the CSG conductive trench 5 does not reach the nO region and a deep doped pocket is implanted between the trench and the nO layer to form the source region of the ST selection transistors. The gate stacks FG / CGe of transistors TE, J, TE, 4 j are covered by a dielectric layer D3 on which the bit line EBL 1 extends. Cl contacts pass through the layer D3 to electrically connect the bit line EBL, to the drain regions n2 (D) of the transistors TE, J, TE, 4 ,,. The conductive regions IS of the transistors TE, 4 ,, are here doped regions n1 of the substrate which extend under the floating gates FG, between the drain regions n2 and source n3 of the transistors TE, J, TE, 4 j, and are therefore covered by the tunnel dielectric layer D1. The dielectric layers DO, D1, D2 and D3 are, for example, silicon dioxide SiO2. FIG. 4 is a sectional view of the floating gate transistors TR, J, TR, 4 of the memory cells C ,, ', C, _i j and their respective selection transistors ST. The structure of these transistors is essentially identical to that of transistors TE, J, TE, 4 and will not be described again. The control gates CGe of these transistors are formed by the polysilicon pieces forming the CGL gate control lines CGL, 4 and their floating gates FG are formed by the same pieces of polysilicon as those which form the floating gates of the transistors TE. , J, TE, 4 j (Fig. 3). Their drain regions n2 (D) are connected by contacts C1 to the RBL bit line, which extends over the dielectric layer D3.
[0026] The transistors TR, J, TR, 4 j differ from transistors TE, J, TE, 4 in that they do not include the conductive region IS extending under the floating gate FG. Thus, when these transistors are biased by a suitable gate voltage, a conductive channel CH1 or CH1 'may be formed between the drain region n2 (D) and the source region n3 (S). A vertical conducting channel CH2 or CH2 'may also be formed between the drain regions n3 (D) and source (S) of the selection transistor ST if the common vertical gate CSG of these transistors simultaneously receives a bias voltage. More particularly, the vertical channel region CH2 of the selection transistor ST of the memory cell extends opposite a first face of the buried vertical control gate CSG, and the vertical channel region CH2 'of the selection transistor. ST of the memory cell C, 4 j extends in view of a second face of the buried vertical control gate, and therefore in front of the channel region CH 2 of the selection transistor of the memory cell Ci, j . The transistors TRIJ, j may also differ from the transistors TEIJ, TE1-ij by the thickness of their tunnel dielectric layer D1, which may be different from that which extends under the floating gates of the transistors TEIJ, j, this choice being provided to those skilled in the art depending on the method of programming the memory cells that will be retained, namely by Fowler-Nordheim effect by means of TEIJ transistors, j or by hot electron injection by means of TRIJ transistors, j both of these options are described below. Unlike transistors TRIJ, j, transistors TEIJ can not have a conductive channel CH1 controlled by the voltage applied thereto, since the region extending between their drain regions n2 and source n3 is short. circuit 15 by the n1 doped region (Fig. 3). These transistors are therefore always on regardless of their gate voltage, and can not be used to read memory cells Cij, j. However, they can be used to erase memory cells under conditions where no drain-source current passes through them, ie by Fowler-Nordheim effect. They can also be used to program the memory cells under conditions where no drain-source current passes through them, also by the Fowler-Nordheim effect, as will be seen later. As a result, the selection transistors ST associated with the TEIJ transistors are not used and are only present here to rationalize the fabrication of the memory cells, in accordance with one embodiment of a manufacturing method described below. It may indeed be simpler to make a useless transistor within a set of transistors used, when the non-realization of the useless transistor would involve additional masking and photolithography steps. As, on the one hand, these selection transistors are on when the word line WL14,1 to which they are connected receives a positive voltage, and, on the other hand, the floating gate transistors TEIJ, j are always on. Because of their region IS, it should be ensured, when designing the memory control devices, that the corresponding bit line EBLJ can not simultaneously receive a voltage other than zero.
[0027] In summary, the TEIJ transistor can be used as an erase transistor of the memory cell C1J by the Fowler-Nordheim effect, which consists of a static programming without programming current, while the transistor TRIJ can be used as a transistor. reading of the memory cell. Similarly, the transistor TE 4 j can be used as an erase transistor of the memory cell Ci_i j by the Fowler-Nordheim effect and the transistor TRi_i j can be used as the read transistor of the memory cell. The RBLJ bit line may be used as the read bit line and the EBLJ goal line as the erase bit line of the memory cell Cij or the memory cell Ci_u. With regard to the programming of the memory cells CI, Ci_i j, embodiments of the invention provide two methods, at the choice of those skilled in the art, namely a Fowler-Nordheim effect programming method. by means of the erase transistor TEIJ or TEl_i j, or a method of programming by hot electron injection by means of the read transistor TRIJ or TE1-1, J. Methods for erasing, programming and reading cells of the memory array MA1 will be described in the following, assuming by way of example that it is desired to erase, program and read the memory cell C1J. Deletion of a memory cell by Fowler-Nordheim effect via the erase transistor TEij A method of erasing the memory cell CI without erasing the memory cell j, via the erase transistor TEIJ, is described by the table 1 of the Appendix, which forms an integral part of the description.
[0028] Figures 5 and 6 illustrate this erasure method. Figure 5 is the circuit diagram of Figure 2 in which the voltage values in Table 1 have been reported. FIG. 6 is a sectional view of transistors TEIJ, identical to that of FIG. 3, in which the voltage values shown in table 1 have been reported.
[0029] The conductive region IS of the TEIJ transistor is raised to the positive voltage EBLV applied to the bit line EBLJ, here 6V, via the contact C1 and the drain region n1 (D) of the transistor. The control gate CGe of the transistor TEIJ being brought to the negative voltage CGV1, here -8V, there appears between this control gate and the conductive region IS a voltage difference dV equal to -14V (FIG. electron extraction of the floating gate FGe by Fowler-Nordheim effect, which puts the TEIJ transistor in the erased state. Since the bit line RBLJ connected to the floating gate transistor TRIJ is at high impedance, this transistor plays no part in the erasing process of the memory cell. The floating gate of the transistor TR, J, however, being electrically connected to that of the transistor TE, J, the transfer of electric charges also causes the erasure of the transistor TR, J, the memory cell as a whole being thus erased via of transistor TE, J. The conductive region IS of the transistor TE, _, j of the twin memory cell C, _, j is also raised to the positive voltage EBLV applied to the bit line EBL ,, here 6V, via the contact Cl and the drain region n1 (D) of the transistor. Since the control gate CGe of the transistor is brought to the positive voltage CGV, _, here 3V, a difference in voltage dV equal to -3V appears between this control gate and the conductive region IS, which is insufficient to extract electrons of the floating gate of the transistor. The twin memory cell C, _, is thus not erased.
[0030] This memory map and memory cell structure thus allows individual erasure of each memory cell, ie bit erasure. This possibility makes it possible to carry out indifferently a memory erasable by bit, word or page without modifying the general structure of the memory plane or its control organs.
[0031] FIG. 7 is a sectional view of two transistors TE, +1, TE, _, j +, of two memory cells C ,,, + 1, (not shown in FIG. 2 or FIG. 5) which contiguously with the memory cells C , J, C, _ ,,,. The memory cells C ,,, + 1, are connected to the same word line WL, _ ,,, as the memory cells C, J, C, _ ,,, but are connected to a different bit line EBL, + , which receives the default voltage EBLV *, here OV. The transistors TE, J + 1, TE, _, j + have their control gates CGe connected to the same gate control lines CGL 'CGL, _, as the transistors TE, J, TE, _, j and thus receive the same voltages CGV 'here -8V, and CGV, _ ,, here 3V. Thus, the voltage difference dV between the control gate CGe of the transistor TE, J + and its conducting region IS is equal to -8V and this transistor undergoes an erase stress, that is to say a parasitic erasure of low intensity which could, if the transistor was in the programmed state, and after many erase cycles of other memory cells connected to the gate control lines CGL 'CGL, _ ,, substantially alter its threshold voltage and therefore lead to a corruption of its state, and therefore a corruption of the data bit associated with the programmed state.
[0032] Furthermore, the voltage difference dV between the control gate CGe of the transistor TE, _,, +, and its conducting region IS is 3V and this transistor undergoes no erasure stress, the control line CGL gate, being brought to only 3V. Similarly, default voltages applied to the memory cells connected to other word lines WL (not shown in the figures) do not cause erasure stress in these memory cells.
[0033] Ultimately, the erasing method according to the invention not only allows individual erasure of each memory cell, but also limits the occurrence of erasure stress to memory cells connected to the same gate control line. while various other known erasure methods, allowing only word, if not page, deletion also cause erasure stress to the memory cells connected to other word lines. Management of erasure stress, by methods known per se of refreshing the memory cells, is therefore simplified, given the reduced number of memory cells to be refreshed. For example, it will be possible to initiate a refresh sequence for the memory cells of a word line after N 15 memory cell programming cycles of this word line, by providing an erase cycle counter associated with the line of the word line. word. Programming of a memory cell by Fowler-Nordheim effect via the erase transistor TEij A method of programming the memory cell without programming of the memory cell C, _, j, via the erase transistor TE, J, is described in Table 2 in the Annex. Figures 8 and 9 illustrate this programming method. Figure 8 is the electrical diagram of Figure 2 in which the voltage values in Table 2 have been reported. FIG. 9 is a sectional view of the TE, J, TE, j transistors identical to that of FIG. 3, in which the voltage values shown in Table 2 have been reported.
[0034] The conducting region IS of the transistor TE, J is brought to the voltage EBLV applied to the bit line EBL, here OV, via the contact C1 and the drain region n1 (D) of the transistor. Since the control gate CGe of the transistor TE, J is raised to the positive voltage CGV 'here 14V, a positive voltage difference dV equal to 14V appears between this control gate and the conductive region IS (FIG. electron injection 35 in the floating gate FGe by Fowler-Nordheim effect, which puts the transistor TE, J in the programmed state. Since the RBL bit line, connected to the floating gate transistor TR, J is high impedance, this transistor plays no part in the programming process of the memory cell. Since the floating gate of the transistor TR, J is however electrically connected to that of the transistor TE, J, the transfer of electric charges also causes the programming of the transistor TR, J, the memory cell Cij as a whole being thus programmed via of transistor TE, J. The conducting region IS of the transistor TE, _, j of the twin memory cell C, _, j is brought to the voltage EBLV applied to the bit line EBLJ, here OV, via the contact Cl and the region of drain n1 (D) of the transistor. The control gate CGe of the transistor 10 TE, _, j being brought to the positive voltage CGV, _ ,, here 3V, there appears between this control gate and the conductive region IS a voltage difference dV equal to 3V, which is insufficient to inject electrons from the floating gate of the transistor. The twin memory cell C, _ is therefore not programmed.
[0035] FIG. 10 is a sectional view of transistors TE, J + 1, TE, _, j +, neighboring memory cells C, J + 1, C, _, j +, already described in relation to FIG. 7, connected to FIG. the same word line WL, _ ,,, as the memory cells C, _ ,,, but connected to the neighboring bit line EBLJ +, which receives the default voltage EBLV *, here 6V. The transistors TE, J + 1, TE, _, j_p, have their control gates CGe connected to the same gate control lines CGL 'CGL, _, as the transistors TE, J, TE, _, j and thus receive the same voltages CGV 'here 14V, and CGV, _ ,, here 3V. Thus, the voltage difference dV between the control gate CGe of the transistor TE, J + and its conducting region IS is 8V and this transistor undergoes a programming stress, that is to say a spurious programming of low intensity.
[0036] Furthermore, the voltage difference dV between the control gate CGe of the transistor TE, _, j +, and its conducting region IS is 3V and this transistor undergoes no programming stress, the gate control line CGL, _ , being raised to only 3V. Likewise, default voltages applied to memory cells connected to other word lines WL (not shown in the figures) do not cause any programming stress in these memory cells. Ultimately, this programming method, like the erasing method previously described, only causes electrical stress to memory cells connected to the same gate control line, the effects of which can be neutralized by a method of refreshing the gate. type mentioned above.
[0037] 3021804 16 Programming of a memory cell by injection of hot electrons via the read transistor TRij A programming method of the memory cell without programming of the memory cell C, _i j, via the read transistor TR, J, is described in Table 3 in the Annex. Figures 11 and 12 illustrate this programming method. Figure 11 is the circuit diagram of Figure 2 in which the voltage values in Table 3 have been reported. FIG. 12 is a sectional view of the transistors TR, J, TR, 4 j identical to that of FIG. 4, in which the voltage values shown in Table 3 have been reported. The transistor TR, J receives the positive voltage CGV 'here 10V, on its control gate and is in the on state, the conductive channel CH1 appearing in the substrate PW under the gate stack FG / CGr. The selection transistor ST associated with the transistor TR, J receives the positive selection voltage SV, here 1 to 2V, on its buried vertical grid CSG, and is in the on state, the vertical conductive channel CH2 appearing in front of the CSG gate . Since the RBL bit line is raised to the positive voltage RBLV, here 4V, and the source line SL is connected to the ground (0V), a current flows from the bit line to the source line 20 through the transistor TR, J and the corresponding selection transistor ST. This current corresponds to an electron flow HE shown in FIG. 12, in the opposite direction of the current. This electron flow contains electrons with high kinetic energy (hot electrons) that bypass the n3 doped region ("cold" region). Some of these electrons are injected into the floating gate at an injection point HI, causing the programming of the transistor TR, J, as well as the programming of the erase transistor TE, J which plays no part in the process of programming. The transistor TR, 4 j of the twin cell, however, receives the voltage CGV, 4 which is equal to OV, so that it undergoes no spurious programming process, nor any of the other transistors for reading the memory plane, which does not receive only zero voltages.
[0038] Reading a memory cell via the read transistor TRij A method of reading the memory cell C1j via the read transistor TR, J, is described in Table 4 in the Appendix.
[0039] Figures 13 and 14 illustrate this reading method. Figure 13 is the circuit diagram of Figure 2 in which the voltage values in Table 4 have been reported. FIG. 14 is a sectional view of the transistors TR, J, TR, 4 j identical to that of FIG. 4, in which the voltage values appearing in table 4 have been reported.
[0040] The transistor TR, J receives the positive voltage CGV 'here from 2 to 3V, which is lower than the threshold voltage of the programmed transistor but greater than the threshold voltage of the erased transistor. If the transistor TR, J is in the erased state, that is to say if it has a threshold voltage Vt lower than the voltage CGV 'the conductive channel CH1 appears in the substrate 10 PW, under the stack FG / CGr grid. The selection transistor ST associated with the transistor TR, J receives the positive selection voltage SV, here 3V, on its buried vertical grid CSG, and is in the on state, the vertical conductive channel CH2 appearing in front of the buried gate CSG. Since the bit line RBL is raised to the positive voltage RBLV, here 1V, and the source line SL is connected to the ground (0V), the transistor TR, J is traversed by a read current Ir which flows from the bit line to the source line. This current Ir is against zero if the transistor TR, J is in the programmed state, that is to say if it has a threshold voltage greater than the voltage CGV. A current amplifier (not shown) connected to the RBL bit line, makes it possible to detect the presence or absence of the current Ir, and to deduce the erased or programmed state of the transistor TR, J, to which a logic value , 0 or 20 1, is assigned by convention. The transistor TR, 4 j of the twin memory cell receives the negative voltage CGV, 4, here -2V. This transistor, if it is in the erased state, may have a threshold voltage close to zero. Applying a negative gate control voltage ensures that it remains in the off state. Indeed, this transistor being connected to the same RBL bit line, the transistor TR, J being read, its turning on could corrupt the reading of the transistor TR, J. Figures 15 to 22 show steps of a method of manufacturing memory cells 30 j, Ci_i j previously described. FIG. 15 shows a preliminary stage of formation in the PW substrate of three STIO, ST1, ST2 insulation trenches of STI type ("Shallow Trench Insolation") which delimit two substrate strips 51, S2 in which the memory cells are going to be performed. This step is preceded by a step of implantation in the substrate of the buried layer nO forming a source plane (not visible in the figure) or implantation of several source lines. A source plane is generally preferred to multiple source lines if it is intended to erase the memory cells by hot electron injection. During a step shown in FIG. 16, a conductive trench is formed transversely to the strips S1, S2 by etching the substrate, depositing the dielectric layer OD (not visible) and depositing a PO polysilicon layer and engraving of it. The trench is intended to form both the word line WL, 4 ,, and the buried vertical control gate of the selection transistors ST of the memory cells.
[0041] During a step shown in FIG. 17, the substrate band S2 is doped by implantation of N-type dopants, the substrate band S1 being masked during this operation. This step makes it possible to carry out the conducting region IS which will extend under the floating gate of the erase transistors TEIJ, TE1-1, J.
[0042] During a step shown in FIG. 18, the tunnel dielectric layer D1 previously described is deposited on the substrate PW, then a polysilicon band P1, intended to form floating gates, is deposited on the substrate strips S1 and S2. During a step shown in FIG. 19, the dielectric layer D2 is deposited on the substrate PW, then a layer of polysilicon P2 is deposited on the layer D2. The layer P2 is then etched with the layer D2 as well as with the layer P1 to form the gate control lines CGL1, CGLi_i, and, beneath it, the CFG common floating gates, resulting from the simultaneous etching of the layer Pl.
[0043] In a step shown in Fig. 20 the substrate strips Si, S2 are doped by self-dopant implantation aligned on the gate control lines CGL1, CGLI4 and on the word line WL14,1, the band of substrate S2 is therefore doped a second time. This step reveals the source S and drain D regions of the transistors TRIJ, TE1J, j, as well as the drain regions of the selection transistors ST.
[0044] During a step shown in FIG. 21, the dielectric layer D3 is deposited on the substrate and holes are made in the layer D3, then metallized to form the contacts C1. Cl contacts extend above D drain regions of the TRIJ transistors, and others above the drain regions D of the TEIJ transistors. During a step shown in FIG. 22, a metal layer M1 ("metal 1" ) is deposited on the substrate and is etched to obtain two conductive strips which form the bit lines RBLJ and EBLJ, the first being arranged on the contacts Cl made above the drain regions D of the transistors TRIJ, j and the second arranged 5 is identical to FIG. 22 and shows the occupied area in width W and in length L by each memory cell C1J, j, the assembly forming the contact 5 made above the drain regions D of the TEIJ transistors. a "brick of stockings e "20 of the memory plane, containing two twin dual cells, the repetition of which allows the design of a memory array MA1 of variable size chosen according to the intended application. The contacts C1 being in this case shared by memory cells made above and below memory cells Cij, Ci_u ("above" and "below" in the plane of the figure), which are not shown only half of the area occupied by the Cl contacts is considered to be part of the "base brick" 20.
[0045] Although these memory cells CI, J, j have a surface area double that shown in FIG. 1, it will be appreciated by those skilled in the art that the semiconductor surface they occupy is not very different from that occupied by them. conventional memory cells having "planar" type selection transistors that are not shared, because the buried vertical selection grids greatly reduce their area and even more so that they are shared. Furthermore, in one embodiment of the invention, a memory array according to the invention may comprise a first memory zone made from memory cells as described in FIG. 1, forming an erasable mass memory per page. and a second memory zone made from memory cells according to the invention, forming a bit-wise or word-erasable data memory, offering a finer erasure granularity than the mass memory and more suitable for certain applications.
[0046] FIG. 24 is a sectional view of the memory cell Cij according to a section plane AA 'shown in FIG. 23 and perpendicular to the sectional plane of FIGS. 3 and 4, together showing the transistors TRIJ, TEIJ and their common floating gate FGT. This figure also shows that it is possible to further reduce the width W of the memory cell by reducing the width of the central isolating trench STIO which separates the transistors TRIJ, TEIJ, this insulating trench does not need to present the insulation width usually used for trenches STI1, STI2 which separate neighboring memory cells, since transistors TR, J, TE, J are electrically coupled. FIG. 25 is the electrical diagram of a memory MEM1 comprising the memory plane MA1 according to the invention, only the cells Ci_i j being represented. The memory comprises a control circuit CCT1, a word line decoder RD1, a column decoder CD1, reading amplifiers SA in number equal to the number of bits of a word DTR to be read in the memory, for example a word of eight bits BO-B7, and BLT1 programming latches for applying voltages to the RBL or EBL bit lines, depending on a DTW word to be written to the memory, for example an eight bit word BO-B7 . The RD1 word line decoder controls the voltages applied to the CGL gate control lines' CGL, 4 and to the word line WL, 4 ,, as a function of a most significant address A (n-1) -A (x) a word, or line address. The decoder CD1, in combination with the latches BLT1, controls the voltages applied to the bit lines RBL, EBL, as a function of a low-order address A (x-1) -A (0) of the word, or address column, the row and column addresses together forming the address A (n-1) -A0 of a word to read or write in the memory plane. In read mode, the decoder CD1 connects the SA amplifiers to the RBL bit lines, connected to the memory cells to be read, and the read amplifiers provide the DTR word. The circuit CCT1 comprises, for example, a CPU, a VGEN voltage generator, and address and data registers. It executes read or write commands, controls the decoders, provides the voltages necessary for the read or write operations (erasure-programming), the supply of the high and low order addresses to the decoders , and if necessary runs a program for refreshing memory cells. Although the improvement just described was originally designed to be applied to a memory cell structure of the type shown in FIG. 1, it will be apparent to those skilled in the art that embodiments of this enhancements may apply to other types of memory cells. By way of example, FIG. 26 shows an embodiment of this improvement applied to memory cells without selection transistor. The memory plane MA1 'represented comprises memory cells C, 4 ,, each comprising a floating gate transistor TRIJ, respectively TRi_i j and a floating gate transistor TEIJ, respectively TEl_i j, of the same structure as those described above. The transistor TRIJ has a drain terminal connected to the RBLJ bit line, a control gate CGr connected to the word line WL1, and a source terminal connected directly to the source line SL.
[0047] The TEIJ transistor comprises a drain terminal connected to the EBLJ bit line, a CGr control gate connected to the word line WL1, and an unconnected source terminal. As previously, the floating gate FGr of the transistor TRIJ is electrically connected to the floating gate FGe of the transistor TEIJ and the latter comprises the conducting region IS facing its floating gate, allowing the memory cell to be erased. The memory cell Cl_i j has an identical structure and the description above applies by replacing the index i by the index i-1. Still other variants could be provided, for example by removing the source terminal of the TEIJ transistors, in the embodiment of FIG. 26 or in the embodiment of FIG. 2, or by omitting the selection transistors. ST associated with transistors TEIJ, j in the embodiment of FIG. 2. FIG. 27 is the electrical diagram of a memory plane MA2 comprising two memory cells Cij, Cij-pi according to a second improvement of the memory plane structure and 1, this improvement being implemented here in combination with the improvement previously described in relation with FIG. 2. The memory cells are accessible for reading and writing via a first bit line RBLJ, a second line RBLi-pi bit, third EBLJ bit line j + i, one WLI word line and two CGL11, CGL21 gate control lines. The memory cell CI belongs to a physical page P1 of the memory plane and the memory cell Ci_u belongs to an adjacent physical page P1_1. The pages PI, 1314 may include various other memory cells and the memory plane MA1 may comprise various other pages.
[0048] According to the preceding improvement, the memory cell Cij comprises two floating gate transistors TRIJ, TEIJ whose floating gates FGr, FGe are interconnected, the floating gate transistor TRIJ being dedicated to the reading of the transistor memory cell and the gate transistor floating TEIJ dedicated to erasing the memory cell. As before, the floating gates FGr, FGe can be formed by the same conductive element CFG and each transistor TRIJ, TEIJ comprises a conductive region IS which extends opposite its floating gate via a layer of tunnel oxide. The transistor TRIJ has a control gate CGr connected to the gate control line CGL11, a drain terminal D connected to the bit line RBLJ and a source terminal S connected to the drain terminal D of a transistor. ST selection whose source terminal S is connected to a source line SL. The floating gate transistor TEIJ has a control gate CGe connected to the gate control line CGL11, a drain terminal D connected to the EBLJ j-pi bit line and a source terminal S connected to the drain terminal 10 D of a selection transistor ST whose source terminal S is connected to a source line SL. The memory cell CI J + i has the same structure as the memory cell CI, and comprises two floating gate transistors TRIJ-pi, TE1J-pi whose floating gates FGr, FGe are interconnected or formed by the same conductive element CFG. The transistor TR1J + 1 has a control gate CGr connected to the gate control line CGL21, a drain terminal D connected to the bit line RBLJ + 1 and a source terminal S connected to the drain terminal D d a selection transistor ST whose source terminal S is connected to a source line SL. The floating gate transistor TE1J + 1 has a control gate CGe connected to the gate control line CGL11, a drain terminal D connected to the bit line EBLJJ-pi and a source terminal S connected to the gate terminal. drain D of a selection transistor ST whose source terminal S is connected to a source line SL. The selection transistors ST associated with the floating gate transistors TRIJ, TR1J + 1 have a buried vertical common control gate CSG. Likewise, the selection transistors ST associated with the floating gate transistors TEIJ, TE1J + 1 have a buried vertical common control gate CSG. The memory plane MA2 thus differs from the memory plane MAI of FIG. 2 in that the transistors TRIJ, TR1J + 1 of the twin memory cells CI J, J + i are connected to different bit lines RBLJ, RBLJ + 1. As will be seen below, these two bit lines make it possible to implement a method of reading memory cells that does not require, during the reading of a memory cell, to apply a negative voltage to the control line of the memory. CGL11 or CGL2 grid of the twin memory cell.
[0049] It will be noted in advance that the addition of an additional bit line in a structure of two twin memory cells as shown in FIG. 1 involves an increase in the area of the pair of memory cells, considered as "basic brick" of a memory plane, because it does not allow to receive two lines of bit. In contrast, a structure of two twin dual memory cells of the type shown in FIG. 2 makes it possible to provide the two bit lines RBLJ, RBLJ + 1 dedicated to reading the memory cells in addition to the bit line EBLJ j + i dedicated to erasing memory cells, without increasing their area. This will be shown in relation with FIGS. 28 to 32, which show a variant of the manufacturing method previously described of a pair of memory cells forming a "basic brick" of the memory plane, this variant making it possible to produce the two lines of RBLJ bit, RBLJ + 1 instead of the RBLJ bit line without increasing the area of the pair of memory cells. The initial steps of the manufacturing process, previously described in connection with FIGS. 15 to 21, are not modified. The step of FIG. 22, of making the bit lines RBLJ, EBLJ, is replaced by the step shown in FIG. 28. During the step of FIG. 28, a metal layer M1 ("metal 1" ) is deposited on the substrate and is etched to obtain on the one hand a conductive strip which here forms the EBLJ j-pi bit line (previously designated EBLJ) and on the other hand two conductive rectangles parallel to the EBLJ bit line. J + i, which form two sections of bit lines P1 (RBLJ), P1 (RBLJ + 1). These two sections of bit lines extend above the contacts C1 which have been made above the drain regions D of the transistors TR, J, TR, J + 1 during the step shown in FIG. .
[0050] In a step shown in Fig. 29, a dielectric layer D4 is deposited on the substrate, and orifices are made in the layer D4 above the sections of bit lines P1 (RBLJ), P1 (RBLJ + 1) and then metallized to form the C2 contacts.
[0051] During a step shown in FIG. 30, a metallic layer M2 ("metal 2") is deposited on the substrate and then etched to obtain two other conducting rectangles forming two sections of P2 bit lines (RBLJ), P2 (RBLi + i) perpendicular to the sections Pl (RBLJ), Pl (RBLi + i) and which extend above the contacts C2.
[0052] During a step shown in FIG. 31, a dielectric layer D5 is deposited on the substrate, and orifices are made in the layer D5 above the bit line sections P2 (RBLJ), P2 (RBLJ). +1), then metallized to form the contacts C3.
[0053] In a step shown in Fig. 32, a metal layer M3 ("metal 3") is deposited on the substrate and is etched to obtain two conductive strips which form the RBLJ and RBLJ + 1 bit lines, the first being arranged on the contacts C3 connected to the drain region D of the transistor TR, J, and the second arranged on the contacts C3 connected to the drain region D of the transistor TR, J + 1. As shown in Fig. 32, the bit lines RBLJ and RBLJ + 1 are parallel to the bit line EBLJ j + i, which is two metal levels below them, and the set goes into the template cells C, J, C, J + i without requiring an increase in their area. The memory cells are programmed and erased as previously described. They are read by means of bit lines RBLJ, RBLJ + 1 in a manner to be described. Reading a memory cell via a bit line RBLi or RBLi-Ei A method of reading the memory cell C, J of FIG. 27 via the read transistor TR, j and the bit line RBLJ is described by FIG. Table 5 in the Annex. Fig. 33 is an electrical diagram similar to that of Fig. 27 in which the voltage values in Table 5 have been reported. The transistor TRij receives on its control gate the positive voltage CGV1i, here from 2 to 3V, and turns on if it is in the erased state. The selection transistor ST associated with the transistor TRij receives the positive selection voltage SV on its control gate, here 3V, and is in the on state. Since the bit line RBLi is raised to the positive voltage RBLV 1, here 1 V, and the source line SL is connected to the ground (0 V), the transistor TRij is traversed by a read current Ir flows from the bit line to the source line. The transistor TRI & + i of the twin memory cell receives the zero voltage CGV2i. This transistor, if it is in the erased state, may have a threshold voltage close to zero or even negative and switch into the on state. Indeed, the bit line RBLi-pi is not connected to any sense amplifier during the reading of the transistor TRij and the transistor TRI & + i is not read. Thus, even in the absence of a negative voltage on the gate control line CGL2i, the transistor TRI & + i can not corrupt the reading of the transistor TRij, and vice versa when reading the transistor TRi 3021804 FIG. 34 is the electrical diagram of a memory MEM2 comprising a memory plane MA2 according to the invention, only cells C, J + 1 being represented. The memory includes a CCT2 control circuit, a RD2 word line decoder, a CD2 column decoder, SA sense amplifiers, and BLT2 program locks. The word line decoder RD2 controls the voltages applied to the gate control lines CGL1 'CGL2, and to the word line WL, as a function of a most significant address A (n-1) -A (x) d a word (line address). The decoder CD2, in combination with the 10 locks BLT1, controls the voltages applied to the bit lines RBL, RBL, + 1, EBL, J +, as a function of the column address A (x-1) -A (0 ) the word. In read mode, the decoder CD2 connects the sense amplifiers SA to the RBL bit lines, connected to the memory cells to be read, and the sense amplifiers provide a read word DTR in the memory, for example 8 bits BO-B7. The circuit CCT2 comprises, as the circuit CCT1 previously described, a CPU, a VGEN voltage generator, and address and data registers. It executes read or write commands, controls decoders, provides the necessary voltages for read or write operations (erasure-programming), the supply of high and low-weight addresses, and if necessary executes a program for refreshing the memory cells. In one embodiment, the word line decoder RD2 is configured to separately control the voltages applied to the twin gate control lines CGL1 'CGL2' which here have the same high-order address A (n-1) -A (x). This separate control of the voltages can be reserved for the erase operations, to apply a positive voltage to these memory cells located on a twin page of that containing the memory cell (s) being erased (see Figs 6 and 7). ). In read mode, however, the decoder can apply the same voltage to the twin grid control lines CGL1 'CGL2, or even to all the grid control lines of the memory plane to limit logic gate switching and thus limit power consumption. of the memory, because the selection of memory cells for reading is ensured by means of word lines WL. In such an embodiment, the decoder RD2 receives, in addition to the most significant address A (n-1) -A (x) of a word, the least significant bit A (0) of the low-order address A (x-1) - A (0) of the word. The decoder RD2 also receives from the circuit CCT2 an information signal EPR which indicates to it whether the address decoding to be performed is involved in the context of reading, erasing or programming of memory cells. If decoding occurs as part of an erasure, the decoder RD2 differentiates the two gate control lines CGL1 'CGL2, as a function of the bit A (0). In other words, the decoder RD2 selects the gate control line CGL1, if the bit line RBL, is designated by the complete address received by the memory, or selects the gate control line CGL2, if the RBL bit line, +, is designated by the full address received by the memory. In an equivalent variant, the decoder may receive a signal from the column decoder CD2, indicating which of the two grid control lines must be selected. 1 () One skilled in the art can naturally provide other embodiments of the decoder, for example to control separately the voltages applied to the CGL1 CGL2 twin grid control lines, reading, programming and erasure. Although the second improvement which has just been described was initially designed to be applied to a memory cell structure according to the first improvement, as shown in FIG. 2, it will be apparent to one skilled in the art that embodiments of this second improvement can be applied to other types of memory cells.
[0054] By way of example, FIG. 35 shows an example of application of the second improvement to the memory cell structure shown in FIG. 1, and shows a memory plane MA2 'comprising four memory cells D, J + 1, D, J + 1, D, J + 3 of the same structure and layout as the cells Mij, M, -, j, M, j + 1, j +, of FIG. 1, but considered as being part of the same logical page that is, having the same high-order address. The memory cells Dij, are thus twin memory cells and share the same selection grid CSG. The memory cells Di j + 2, Di j + 3 are twin memory cells and share the same CSG selection grid. The control gates of the floating gate transistors T, J, T, J + 2 of the memory cells Di j, Di j + 2 are connected to the gate control line CGL1, and the control gates 30 of the floating gate transistors T, J + 1, T, J + 3 memory cells D, J + 1, D, J + 3 are connected to the gate control line CGL2 ,. The drain terminals of the twin memory cells Dij, D, J + 1, instead of being connected to the same bit line, are connected to different bit lines BL ,, BL, + ,. Similarly, the drain terminals of the twin memory cells D, J + 2, D, J + 3, instead of being connected to the same bit line, are connected to different bit lines BL, + 2, BL + 3.
[0055] 3021804 27 APPENDIX Table 1: Fowler-Nordheim erasure of Cià via TE ,,,, Figs. 5 and 6 Ref. Description Sign Example GTC; Erase voltage applied to the CGL control grid; transistors TRjj, TEjj of the memory cell Cij (memory cell selected by deletion) via the gate control line CGL; negative -8V CGV.-1 Suppression inhibition voltage applied to the control gate CGLi_I transistors TRi_I j, TEi_I j of the memory cell Ci_j j (twin memory cell not selected in erasure) via the gate control line CGL; positive 3V EBLV Erase voltage applied to the EBL bit line; positive 6V RBLV Voltage applied to the RBL bit line; - HZ (*) SV Selection voltage applied to the word line WL._1 ,, common to the twin memory cells C 1 j, Cij - OV SPV Source line voltage applied to all SL source lines (or to the plane of source) - OV VB Electrical potential of PW-OV substrate CGV * Default voltage applied to all other 3V EBLV positive CGL grid control lines * Default voltage applied to non-selected EBL bit lines - OV RBLV * Voltage per fault applied to an unselected RBL bit line (eg "RBL1 + 1") - OV SV * Voltage applied to non-selected WL word lines - OV (*) High impedance, ie line disconnected from the rest of the circuit 5 3021804 28 Table 2: Fowler-Nordheim programming of Cu via TE ,,, Figs. 8 and 9 Ref. Description Sign Example GTC; Voltage applied to the CGL control grid; transistors 14V positive TRjj, TEm of the memory cell Cm (memory cell selected in programming) via the CGL grid control line; CGV.-1 Voltage applied to the CGL control gate; _ I transistors TRi_j j, TEi_j j of the memory cell Ci_i j (twin memory cell not selected in programming) via the gate control line CGL; positive 3V EBLV Voltage applied to the EBL bit line; - OV RBLV Voltage applied to the RBL bit line; - HZ SV Selection voltage applied to word line WL._l ,, common to twin memory cells C 1 j, Cm - OV SPV Source line voltage applied to all SL source lines (or source plane) - OV VB PW-OV substrate electrical potential CGV * Voltage applied to all other 3L EBLV positive CGL grid control lines * Voltage applied to non-selected EBL bit lines - 6V RBLV * Voltage applied to unselected RBL bit lines - HZ SV * Voltage applied to unselected WL word lines - OV 3021804 29 Table 3: Programming of Cià by injection, via TRià, Figs. 11 and 12 Ref. Description Sign Example GTC; Voltage applied to the CGL control grid; positive transistors 10V TRjj, TEm of the memory cell Cm (memory cell selected in programming) via the gate control line CGL; CGV.-1 Voltage applied to the CGL control gate; _ I transistors TRi_j j, TEi_j j of the memory cell Ci_j j (twin memory cell not selected in programming) via the gate control line CGL; - OV EBLV Voltage applied to bit line EBLj - OV or higher RBLV Voltage applied to RBL bit line; positive 4V SV Selection voltage applied to the word line WLi_I j common to the twin memory cells C jj, Cm positive 1-2V SPV Source line voltage applied to all source lines SL (or source plane) - OV VB Electrical potential of PW-OV substrate CGV * Voltage applied to all other gate control lines CGL - OV EBLV * Voltage applied to unselected EBL bit lines - OV RBLV * Voltage applied to unselected RBL bit lines - OV SV * Voltage applied to unselected WL word lines - OV 3021804 Table 4: Reading Ci via TRià, Fig. 13 and 14 Ref. Description Sign Example GTC; Voltage applied to the CGL control grid; transistors TRjj, TEjj of the memory cell Ci j (memory cell selected for reading) via the gate control line CGL; positive 2-3V CGVi_I Voltage applied to the control gate CGLi_I of the transistors TRi_j j, TEi_j j of the memory cell Cil_ j (twin memory cell not selected in reading) via the gate control line CGL; negative -2V EBLV Voltage applied to the EBL bit line; - OV RBLV Voltage applied to the RBL bit line; positive 1V SV Selection voltage applied to the word line WLi_i j common to twin memory cells Cil_ 1, positive Cm 3V SPV Source line voltage applied to all source lines SL (or source plane) - OV VB Potential voltage PW - OV CGV * Voltage applied to all other gate control lines CGL - OV EBLV * Voltage applied to unselected EBL bit lines - OV RBLV * Voltage applied to unselected RBL bit lines - OV SV * Voltage applied to unselected WL word lines - OV 3021804 31 Table 5: Reading Cià via TRià and RBLi, figure 33 Ref. Description Sign Example CGV1i Voltage applied to the CGL1 control gate of the positive 2-3V transistors TRjj, TEjj of the memory cell Ci j (memory cell selected for reading) via the gate control line CGLli CGV2i Voltage applied to the control gate CGL2 of the OV transistors TR41 + 1, TEjj + 1 of the sky memory cell (memory cell not selected for reading) via the grid control line CGL2i EBLV Voltage applied to the bit line EBL; ; +1 - OV RBLV, Voltage applied to the RBL bit line, selected from the 1V positive memory cell pair RBLVj + 1 Voltage applied to the unselected RBLj + bit line of the OV memory cell pair SV Applied selection voltage at the word line WL; common to twin memory cells Ci1 + 1, positive Cile 3V SPV Source line voltage applied to all source lines SL (or source plane) - OV VB Electrical potential of PW-OV substrate CGV * Voltage applied to all other gate control lines CGL - OV EBLV * Voltage applied to non-selected EBL bit lines - OV RBLV * Voltage applied to non-selected RBL bit lines - OV SV * Voltage applied to non-selected WL word lines - OV

权利要求:
Claims (16)
[0001]
REVENDICATIONS1. Non-volatile memory cell (Ci j, Ci_i j, Ci j + i) on a semiconductor substrate (PW), comprising a first floating gate transistor (TRij, TRi_i j, TRij + i) having a control gate (CG) , a floating gate (FGr) and a drain region (D), characterized in that it also comprises: a second floating gate transistor (TEij, TEi_i j, TEij + i) comprising a control gate (CG) , a floating gate (FGe) and a drain region (D), and in that: - the floating gates (FGr, FGe) of the first and second floating gate transistors are electrically connected, and - the second floating gate transistor comprises a conductive region (IS, n1) electrically connected to its drain region (D) and extending opposite its floating gate (FGe) via a tunnel dielectric layer (DI).
[0002]
The memory cell of claim 1, wherein the floating gates of the first and second floating gate transistors are formed by a same layer (CFG) of a conductive material.
[0003]
3. Memory cell according to one of claims 1 and 2, wherein the conductive region (IS, n1) is a doped region of the substrate.
[0004]
4. Memory cell according to one of claims 1 to 3, comprising at least one selection transistor (ST) connecting a source region (S) of the first floating gate transistor (TR, J, j, TRij + i) to a source line (SL).
[0005]
5. Memory cell according to claim 4, wherein the selection transistor comprises a vertical control grid (CSG) buried in the substrate.
[0006]
6. Non-volatile memory (MEM1, MAL MEM2, MA2) on semiconductor substrate (PW), characterized in that it comprises: - at least one memory cell (C, J, Ci_i j, C, j + i) according to one of claims 1 to 5, - a first bit line (RBLJ, RBLi + i) electrically connected to the drain region of the first floating gate transistor (TR, J, j, TR, j + i), and 3021804 33 - a second bit line (EBLi, EBLi j + i) electrically connected to the drain region of the second floating gate transistor (TEij, j, TE +1).
[0007]
7. The memory according to claim 6, comprising means (CCT1, CCT2, RD1, RD2, BLT1, BLT2, CD1, CD2) for erasing the memory cell by the Fowler Nordheim effect, configured to extract negative electric charges from the floating gate (FGe) of the second floating gate transistor (TE4j, TE, 4j, TE1j-pi) through the conductive region (IS, n1). 10
[0008]
8. Memory according to one of claims 6 and 7, comprising means (CCT1, CCT2, RD1, RD2, BLT1, BLT2, CD1, CD2) for programming the memory cell by Fowler Nordheim effect, configured to inject electric charges. negative in the floating gate (FGe) of the second floating gate transistor (TE1j, j, -pi) via the conductive region (IS, n1). 15
[0009]
9. Memory according to one of claims 6 and 7, comprising means (CCT1, CCT2, RD1, RD2, BLT1, BLT2, CD1, CD2) programming the memory cell by injection of hot electrons, configured to inject (HI ) negative electric charges in the floating gate (FGr) of the first floating gate transistor (TRij,, TRIj + i) by means of a current flowing in the transistor.
[0010]
10. Memory according to one of claims 6 to 9, comprising means (CCT1, CCT2, RD1, RD2, BLT1, BLT2, CD1, CD2, SA) for reading the memory cell via the first gate transistor. floating point (TRij, j, TRIj + i). 25
[0011]
11. Memory according to one of claims 6 to 10, comprising a first memory cell (C1j) according to claim 5 and a second memory cell (CI j + i) of the same structure as the first memory cell, having a selection transistor (ST) having the same control gate (CSG) as the selection transistor (ST) of the first memory cell.
[0012]
The memory (MEM2, MA2) of claim 11 comprising: - a bit line (RBLi) electrically connected to the drain region of the first floating gate transistor (TRij) of the first memory cell (Ci j), another bit line (RBLi + i) electrically connected to the drain region of the first floating gate transistor (TRij-pi) of the second memory cell (Ci j + 1), and 3021804 34 - yet another line of bit (EBLi, j + i), electrically connected to both the drain region of the second floating gate transistor (TEij) of the first memory cell (Cij) and to the drain region of the second floating gate transistor (TEij , TEi_i j, TEij + i) of the second memory cell (Ci, i + i). 5
[0013]
13. A method of manufacturing on a semiconductor substrate (PW) of a memory cell according to one of claims 1 to 5, comprising the steps of: - forming in the substrate insulating trenches (STI) delimiting at least one first (S1) and a second (S2) substrate strips, - doping the second substrate strip (S2) to make it conductive, - forming on the substrate a floating gate (FG, P1) arranged transversely to the two substrate strips with the interposition of a first dielectric layer (D1), - forming a control gate (CG, CGL1) on the floating gate with the interposition of a second dielectric layer (D2), to obtain a stack of gates, and 15 - doping the two substrate strips (S1, S2) on each side of the gate stack, to reveal drain (D) and source (S) regions of the first floating gate transistor (TRij, j, TR, j + i) and at least one drain region (D) of the second transistor g floating rille (TE4j, j, TEIj + 1), the conductive region (IS, n1) facing the floating gate of the second floating gate transistor (FG) being formed by a region of the second substrate band (S2) doped before the formation of the stack of grids.
[0014]
14. The manufacturing method according to claim 13, comprising a step of forming in the substrate a conductive trench (P0, CGC, WL-1,1) arranged transversely to the substrate strips (Si, S2) and forming, after doping, two substrate strips (S1, S2), a buried vertical gate (CGC) of a selection transistor (ST) of the memory cell.
[0015]
15. A method of erasing a nonvolatile memory cell (CI j, Cl_i j, j + i) on a semiconductor substrate (PW), the memory cell comprising a first floating gate transistor (TRij, TR4j-pi ) having a control gate (CG), a floating gate (FGr), a tunnel dielectric layer (D1) between the floating gate and the substrate, a drain region (D) and a source region (S), characterized in it comprises the steps of: - providing a second floating gate transistor (TE4j, j, TE1j-pi) having a control gate (CG), a floating gate (FGe) and a drain region (D connecting the floating gates (FGr, FGe) of the first and second floating gate transistors, providing in the second floating gate transistor a conductive region (IS, n1) electrically connected to its drain region (D) and extending opposite its floating gate (FGe) via a dielectric layer tunnel (D1), and - apply a negative electric potential difference (dV) between the control gate 5 of the (CG) and the drain region (D) of the second floating gate transistor (TE1j, TE1-1J, TElj + i), so as to extract negative electric charges from the floating gate (FGe) of the second floating gate transistor (TE1j, j, TElj + i) via the conductive region (IS, n1). 10
[0016]
16. Erasing method according to claim 15, comprising the steps of: - providing a first bit line (RBLi) electrically connected to the drain region of the first floating gate transistor (TRij, TRi_ij, TRij + i), - Provide a second bit line (EBLi, EBLi j + i) electrically connected to the drain region of the second floating gate transistor (TEij, TEi_i j, TEij + i). - providing a gate control line (CGLi) electrically connected to the control gates of the first and second floating gate transistors, and - applying the negative electrical potential difference between the control gate (CG) and the drain region (D ) of the second floating gate transistor (TEij, TEi_i j, TEij + i) via the gate control line (CGLi) and the second bit line (EBLi, EBLij + i).

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同族专利:

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公开号 | 公开日

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US20150348640A1|2015-12-03|

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US20170011804A1|2017-01-12|

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FR3021804B1|2017-09-01|

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优先权:

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申请号 | 申请日 | 专利标题

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FR1454891A|FR3021804B1|2014-05-28|2014-05-28|DUAL NON-VOLATILE MEMORY CELL COMPRISING AN ERASING TRANSISTOR|FR1454891A| FR3021804B1|2014-05-28|2014-05-28|DUAL NON-VOLATILE MEMORY CELL COMPRISING AN ERASING TRANSISTOR|

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US14/724,229| US9484107B2|2014-05-28|2015-05-28|Dual non-volatile memory cell comprising an erase transistor|

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US15/276,462| US9613709B2|2014-05-28|2016-09-26|Dual non-volatile memory cell comprising an erase transistor|